NBTI Product Level Reliability Challenges

INTRODUCTION The gate dielectric has been the subject of constant improvement and innovation since the invention of the MOSFET transistor. The gate oxide is the major transistor component to control the transistor channel underneath with respect to leakage currents as well as saturation drive currents. The demand for higher drive currents and better performance has also pushed the gate oxide thickness towards it material limits, especially as we enter the 65nm technology node. The common candidate for the ultimate gate dielectric, silicon dioxide, is facing its structural boundaries and silicon dioxide/nitride stacks will become main stream for 65nm technologies and beyond. Since the introduction of heavily nitrided gate oxides the NBTI phenomena gained significantly on importance. Extensive work has been published on the NBTI reliability for standard DC test conditions (Vs,Vd,Vb=0.0V) as well as under pulsed conditions. However, the role of hydrogen is still not fully understood [1]. Less work was published on the circuit level reliability degradation due to NBTI and the impact of relaxation. This work is analyzing all possible circuit level biasing conditions, maximum operating temperatures, and operating cycles to understand the impact on the circuit level. A simple analytical reliability model is referenced to estimate the threshold voltage shift during real operation conditions. This additional threshold voltage shift is counting against the design margin budget and, hence, has to be added to the SS corner at elevated temperature in order to evaluate the worst case circuit conditions.